1. Field of the Invention
The present invention relates to a semiconductor memory device, more specifically relates to a semiconductor memory device having a test circuit for detecting leakage of a memory cell transistor in a dynamic random access memory (DRAM).
2. Description of the Background Art
As a conventional test for detecting leakage of a memory cell transistor of a semiconductor memory device, particularly of a DRAM (hereinafter referred to as a disturb refresh test), there has been, for example, a technique as described below.
First, High (or Low) data is written into all memory cells. After a write operation into all the memory cells, a given word line is activated, and then an electric charge of a memory cell is read out onto a bit line perpendicular to the activated word line. The read electric charge is amplified (a read/refresh operation) in a sense amplifier circuit, whereby electric potentials of the bit line and a complimentary bit line respectively become High or Low. The situation is retained only for a time period in which retention of data of the memory cell can be assured (hereinafter referred to as a refresh test period).
Under this situation, a memory cell capacitor connected to a non-selected word line retains High data, and with respect to such memory cell that is connected to a bit line having a Low level, an electric potential difference will be generated between a drain and a source of the memory cell transistor, whereby a subthreshold current is passed through. Here, in the case of a memory cell having a transistor whose threshold voltage is low, a large amount of the subthreshold current passes through, and consequently data cannot be retained within a refresh test time period, and a defective cell will be generated. Therefore, after completion of the refresh test time period, the read operation is performed with respect to a test target memory cell so as to check whether or not data is accurately read out.
However, the electric potentials of the bit line and the complimentary bit line can be set High or Low, with regard to the memory cell connected to the non-selected word line, only on the basis of a memory cell array which includes a group of memory cells and a sense amplifier circuit. Further, the above-described refresh test time period usually tends to be set on the order of several ms or several tens of ms, which is substantially long compared to time periods of read-out and write of data from and into a memory, and thus the disturb refresh test constitutes a large proportion of a total test period of the memory.
To solve such problem, a method for reducing the time period of the above-described disturb refresh test has been adopted based on a method for activating a plurality of word lines simultaneously in accordance with a test mode, or on a simultaneous selection of a plurality of memory cell arrays (see, for example, U.S. Pat. Nos. 5,666,317, 5,574,691, 5,519,659 specification).
Along with process refinement and speedup in recent years, a unit of the memory cell array is scaled down, and as a result, the number of the memory cell arrays are increased. Further, in order to realize a large memory capacity with a small chip area, a memory having a hierarchical bit line structure, for example, a DRAM, has been introduced. In such memory, a plurality of sub-bit line pairs are provided so as to correspond to one main bit line pair, and each of the sub-bit line pairs is connected to the main bit line pair via two selection transistors.
However, in the memory having the above-described hierarchical bit line structure, in the case where a unit of the hierarchical bit line is set as a sub-memory cell array, a sub-bit line in a non-selected sub-memory cell array is electrically separated from a main bit line, even in a common memory cell array. Therefore a sufficient electric potential difference cannot be applied between the source and the drain of the memory cell transistor. Therefore, a test is required on the sub-memory cell array basis, which causes a problem of significant increase in a test time period and a test cost.